#!/usr/bin/tclsh

##Open the files to be read and written
set verilog_file [open test_Controle.v w+]
set table_file [open table.txt]

#Start module declaration
puts $verilog_file "`include \"../codigo/Controle.v\"\n"

puts $verilog_file "module test_Controle ( ) ;\n"

puts $verilog_file "    reg   \[5:0\]   t_op ;"
puts $verilog_file "    reg   \[5:0\]   t_fn ;"
puts $verilog_file "    reg   \[4:0\]   t_rt ;\n"

puts $verilog_file "    wire  \[2:0\]   t_selwsource ;"
puts $verilog_file "    wire  \[1:0\]   t_selregdest ;"
puts $verilog_file "    wire          t_writereg ;"
puts $verilog_file "    wire          t_writeov ;"
puts $verilog_file "    wire          t_selimregb ;"
puts $verilog_file "    wire          t_selsarega ;"
puts $verilog_file "    wire          t_selalushift ;"
puts $verilog_file "    wire  \[2:0\]   t_aluop ;"
puts $verilog_file "    wire          t_unsig ;"
puts $verilog_file "    wire  \[1:0\]   t_shiftop ;"
puts $verilog_file "    wire          t_mshw ;"
puts $verilog_file "    wire          t_lshw ;"
puts $verilog_file "    wire  \[2:0\]   t_msm ;"
puts $verilog_file "    wire  \[2:0\]   t_msl ;"
puts $verilog_file "    wire          t_readmem ;"
puts $verilog_file "    wire          t_writemem ;"
puts $verilog_file "    wire  \[1:0\]   t_selbrjumpz ;"
puts $verilog_file "    wire  \[1:0\]   t_seltipopc ;"
puts $verilog_file "    wire  \[2:0\]   t_compop ;\n"

puts $verilog_file "    Controle t_controle( .op(t_op),"
puts $verilog_file "        .fn(t_fn),"
puts $verilog_file "        .rt(t_rt),"
puts $verilog_file "        .selwsource(t_selwsource),"
puts $verilog_file "        .selregdest(t_selregdest),"
puts $verilog_file "        .writereg(t_writereg),"
puts $verilog_file "        .writeov(t_writeov),"
puts $verilog_file "        .selimregb(t_selimregb),"
puts $verilog_file "        .selsarega(t_selsarega),"
puts $verilog_file "        .selalushift(t_selalushift),"
puts $verilog_file "        .aluop(t_aluop),"
puts $verilog_file "        .unsig(t_unsig),"
puts $verilog_file "        .shiftop(t_shiftop),"
puts $verilog_file "        .mshw(t_mshw),"
puts $verilog_file "        .lshw(t_lshw),"
puts $verilog_file "        .msm(t_msm),"
puts $verilog_file "        .msl(t_msl),"
puts $verilog_file "        .readmem(t_readmem),"
puts $verilog_file "        .writemem(t_writemem),"
puts $verilog_file "        .selbrjumpz(t_selbrjumpz),"
puts $verilog_file "        .seltipopc(t_seltipopc),"
puts $verilog_file "        .compop(t_compop) ) ;\n"

#Start tests declaration
set test_number 1
puts $verilog_file "    initial begin"
while {[gets $table_file line] >= 0} {
    puts $verilog_file "        //Test $test_number"
    puts $verilog_file "        //Table line : $line"
    puts $verilog_file "        t_op = 6'b[string range $line 0 5];"
    puts $verilog_file "        t_fn = 6'b[string range $line 6 11];"
    puts $verilog_file "        t_rt = 5'b[string range $line 12 16];"
    puts $verilog_file "        #1"
    puts $verilog_file "        if (t_selimregb == 1'b[string range $line 17 17]"
    puts $verilog_file "         && t_selsarega == 1'b[string range $line 18 18]"
    puts $verilog_file "         && t_selbrjumpz == 2'b[string range $line 19 20]"
    puts $verilog_file "         && t_selregdest == 2'b[string range $line 21 22]"
    puts $verilog_file "         && t_selwsource == 3'b[string range $line 23 25]"
    puts $verilog_file "         && t_writereg == 1'b[string range $line 26 26]"
    puts $verilog_file "         && t_writeov == 1'b[string range $line 27 27]"
    puts $verilog_file "         && t_unsig == 1'b[string range $line 28 28]"
    puts $verilog_file "         && t_shiftop == 2'b[string range $line 29 30]"
    puts $verilog_file "         && t_aluop == 3'b[string range $line 31 33]"
    puts $verilog_file "         && t_selalushift == 1'b[string range $line 34 34]"
    puts $verilog_file "         && t_compop == 3'b[string range $line 35 37]"
    puts $verilog_file "         && t_seltipopc == 2'b[string range $line 38 39]"
    puts $verilog_file "         && t_readmem == 1'b[string range $line 40 40]"
    puts $verilog_file "         && t_writemem == 1'b[string range $line 41 41]"
    puts $verilog_file "         && t_mshw == 1'b[string range $line 42 42]"
    puts $verilog_file "         && t_lshw == 1'b[string range $line 43 43]"
    puts $verilog_file "         && t_msm == 3'b[string range $line 44 46]"
    puts $verilog_file "         && t_msl == 3'b[string range $line 47 49] ) begin"
    puts $verilog_file "             \$display(\"Test $test_number: ok\");"
    puts $verilog_file "        end else begin" 
    puts $verilog_file "             \$display(\"Test $test_number: ERROR!!!\");"
    puts $verilog_file "             \$display(\"t_op = %b, t_fn = %b, t_rt = %b\", t_op, t_fn, t_rt);"
    puts $verilog_file "             \$display(\"t_selimregb = %b, t_selsarega = %b, t_selbrjumpz = %b, t_selregdest = %b, t_selwsource = %b, t_writereg = %b, t_writeov = %b, t_unsig = %b, t_shiftop = %b, t_aluop = %b, t_selalushift = %b, t_compop = %b, t_seltipopc = %b, t_readmem = %b, t_writemem = %b, t_mshw = %b, t_lshw = %b, t_msm = %b, t_msl = %b\", t_selimregb, t_selsarega, t_selbrjumpz, t_selregdest, t_selwsource, t_writereg, t_writeov, t_unsig, t_shiftop, t_aluop, t_selalushift, t_compop, t_seltipopc, t_readmem, t_writemem, t_mshw, t_lshw, t_msm, t_msl);"
    puts $verilog_file "            \$finish;"
    puts $verilog_file "        end\n"
    incr test_number
}
puts $verilog_file "    end"


puts $verilog_file "endmodule"
close $verilog_file
close $table_file
